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A high-throughput architecture is one that maximizes the number of bits per second that can be processed by a design. Unrolling an iterative loop increases throughput. The penalty for unrolling an iterative loop is a proportional increase in area. A low-latency architecture is one that minimizes the delay from the input of a module to the output. Latency can be reduced by removing pipeline registers. The penalty for removing pipeline registers is an increase in combinatorial delay between registers. Timing refers to the clock speed of a design. A design meets timing when the maximum delay between any two sequential elements is smaller than the minimum clock period. Adding register layers improves timing by dividing the critical path into two paths of smaller delay. Separating a logic function into a number of smaller functions that can be evaluated in parallel reduces the path delay to the longest of the substructures. By removing priority encodings where they are not needed, the logic structure is attened, and the path delay is reduced. Register balancing improves timing by moving combinatorial logic from the critical path to an adjacent path. Timing can be improved by reordering paths that are combined with the critical path in such a way that some of the critical path logic is placed closer to the destination register.

r(0)(n) r(0)(n 1..0) 0 r(i)(n) r(i)(n 1..0) division_step r(1)(n..0) division_step r(i+1)(n..0) 0

all timing information is de ned in picoseconds. The timing info for the single LUT is shown as follows.

(continues)

q(p 1)

(CELL (CELLTYPE "X_LUT4") (INSTANCE oDat1) (DELAY (ABSOLUTE (PORT ADR1 ( 499 )) (PORT ADR2 ( 291 )) (PORT ADR3 ( 358 )) (IOPATH ADR0 O ( 519 (IOPATH ADR1 O ( 519 (IOPATH ADR2 O ( 519 (IOPATH ADR3 O ( 519 ) ) )

(continued)

r(1)(n) r(1)(n 1..0)

)) )) )) ))

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benefits procurement, the time and attention left can be used for reflective decision making. Understanding ROI when using consulting services is now more critical than ever, especially at a time when many firms are eliminating benefit advisory services altogether. This rush to meet short-term financials may lead to higher long-term costs with no one at all left to offer a seasoned point of view. The poor economic conditions we have been experiencing the past few years have put a great strain on discretionary budgets. At the same time, while budgets for outside advisers are being cut, the attention, scrutiny, and accountability attached to employee benefit plans has never been higher. Fortunately, how the Internet and other technology developments continue to impact these services on a positive cost-effective basis will be increasingly felt. By attending to wise use of consultants, in conjunction with advancing new technology, you can ensure that your firm reaps truly valueadded service from your consultants as well as utilizing technology as a measurable solution for managing benefits costs. The platform is before us, and it is beckoning us to climb aboard.*

division_step r(2)(n..0)

This SDF entry contains both interconnect and device delay. The SDF speci cation allows interconnect delay to be abstracted as a port delay; that is, only occurring at the input port of a device. The PORT entries of this LUT contain the interconnect delay from the input buffers to the individual inputs of this LUT. The IOPATH entries contain the timing through the LUT. Speci cally, this is the delay from an input to the output and is de ned here to be 519 ps. A simulation with all of these components will provide a very accurate model of the inner workings of the FPGA as real vectors are used to stimulate the design. Not only can this be useful when debugging the design, but it can also be used to uncover other important pieces of information about the design as shown in the following sections.

*From Daniel Cassidy, How to Hire the Right Consultants: Value-Added Benefits Consulting Can Save the Day, Handbook of Business Strategy 2005 (Bradford, W. Yorkshire, England: Emerald Group Publishing, Ltd., October 2004), 225 229.

Node coverage is not frequently applied to gate-level netlists for FPGA design veri cation. Due to the ability of an FPGA to rapidly prototype the design and to run vectors real-time in hardware, the development time for gate-level code coverage is rarely justi ed. That said, code coverage can still be useful at the gate level as it is at the RTL level. When running a gate-level simulation, the code coverage analysis will provide a coverage number relative not to the logical constructs but to the physical elements themselves. One aspect of code coverage at the gate level that can often provide useful information not available through a rapid prototype is that of toggle coverage. Toggle coverage provides not only coverage statistics in the form of covered and not-covered but also in the form of frequency-related information. In the absence of a more sophisticated power analysis tool, designers can use toggle coverage to produce an estimate of power dissipation based on the average

.....

number of toggles per clock cycle, the system voltage, and the average gate capacitance. Pdynamic CV2 f dd (11:1)

r(p 1)(n..0) q(1) r(p 1)(n) r(p 1) (n 1..0)

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